1. Technical Field
The present invention relates to a semiconductor memory apparatus. In particular, the present invention relates to a semiconductor memory apparatus and to a method of resetting the input/output lines of a semiconductor memory apparatus.
2. Related Art
A semiconductor memory apparatus according to the related art will be described with reference to the accompanying drawings.
FIG. 1 is a view showing the layout of an example of a core cell structure of a semiconductor memory apparatus according to the related art. FIG. 2 is a circuit diagram showing the configuration of an I/O switch shown in FIG. 1.
A semiconductor memory apparatus according to the related art includes a predetermined number of unit cell blocks that are arranged at predetermined intervals in column and row directions as shown in FIG. 1.
First input and output lines SIO and SIOB for reading out or writing data from or into corresponding cells are formed at predetermined intervals along the row direction. At least a pair of first input lines SIO and first output lines SIOB are provided. The phase of “SIOB” is opposite to the phase of “SIO”.
Second input and output lines LIO and LIOB for reading out data from the first input and output lines or writing data into the cells through the first input and output lines are formed at predetermined intervals along the column direction. At least a pair of second input lines LIO and second output lines LIOB are provided. The phase of “LIOB” is opposite to the phase of “LIO”.
An I/O switch 11 is formed at each of the nodes where the first input and output lines intersect the second input and output lines.
The detailed connection state and configuration of the I/O switch 11 is as follows. As shown in FIG. 2, a bit line sense amplifier 21 is connected to a bit line BL connected to each cell and a bit line bar BLB having an inverted phase with respect to the bit line. An output terminal of the bit line sense amplifier 21 is connected to the first input and output lines SIO and SIOB. The bit line sense amplifier 21 serves to sense and amplify data on the bit line.
The first input and output lines SIO and SIOB are connected to the second input and output lines LIO and LIOB, respectively. The I/O switch 11 is formed at the node where the first input and output lines SIO and SIOB intersect the second input and output lines LIO and LIOB. The I/O switch 11 has a transistor having a source and a drain connected to “LIO” and “LIOB”, respectively, and a gate through which a second I/O line reset signal LIORST (hereinafter, referred to as a reset signal) is input.
The reset signal is output from a reset driver 12 (FIG. 1).
An IO sense amplifier 22 is connected to the second input and output lines LIO and LIOB, and the output terminal of the IO sense amplifier 22 is connected to a third I/O line GIO. The IO sense amplifier 22 serves to sense and amplify data on the second input and output lines LIO and LIOB.
In the semiconductor memory apparatus according to the related art having the above-mentioned configuration, before a column selection signal for reading out or writing data in placed in an active state, the reset signal LIORST input to the I/O switch 11 by the reset driver 12 is enabled.
Accordingly, each I/O switch 11 conducts a pre-charge operation by short-circuiting the second input and output lines LIO and LIOB according to the reset signal LIORST, which makes it possible to prepare for reading out or writing data.
The reset signal LIORST is disabled while data is read out or written. Accordingly, the I/O switch 11 performs an operation of transmitting data on the second input and output lines LIO and LIOB to the I/O sense amplifier.
The core cell structure of the semiconductor memory apparatus shown in FIG. 1 is configured as a combo type in order to use either all the cells, to use unit cells belonging to any one of the upper and lower half regions where the whole cell region is divided on the basis of the row direction, or to use left and right regions where the upper and lower half regions obtained by dividing the whole cell region on the basis of the row direction are divided on the basis of the column direction.
Specifically, the semiconductor memory apparatus is configured such that a user can use a desired unit cell region by setting an operation mode.
In the case of using unit cells by dividing the whole cell region, for example, in the case of setting an operation mode where the upper half region is used, the unit cells in the lower half region are not used.
However, in the semiconductor memory apparatus according to the related art, reset signals are supplied to all of the I/O switches at predetermined times without distinguishing between the upper and lower regions. Thus, even the I/O switches corresponding to unit cells not concerned with the actual memory operation perform a switching operation according to the reset signals, which causes current consumption and unnecessary power consumption.